library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity BoardTop_tb is
end entity;

architecture simul of BoardTop_tb is
--CONSTANTES
constant	ABUS:integer:=18;  --BUS DE DIRECCION DE LA RAM
constant	DBUS: integer:=16; --BUS DE DATOS DE LA RAM
constant	W: integer:=16; -- # Bits por coordenada
constant	WORDS: integer:=1; --Words por coordenada.

		                 -- 19200 baud, 8 data bits, 1 stop bit
constant	DBIT: integer:=8;               -- # data bits
constant	SB_TICK: integer:=16;   -- # ticks for stop bits. 16/24/32 
constant	DVSR: integer:= 4;    -- baud rate divisor
constant	DVSR_BIT: integer:=8;   -- # bits of DVSR

--UART
signal tick, rx, rx_done_tick: std_logic;
signal rx_dout,tx_din: std_logic_vector(7 downto 0);
signal tx,tx_start, tx_done_tick, tx_start_bis: std_logic;

--INTEFAZ CON MEMORIA
signal ad: std_logic_vector(ABUS-1 downto 0); 
signal we_n, oe_n: std_logic;
signal dio_a: std_logic_vector(DBUS-1 downto 0);
signal ce_a_n, ub_a_n, lb_a_n: std_logic;

--CONTROLES DE SIMULACION
signal clk, reset,mode: std_logic:='0';
signal restart : std_logic;

signal done_delayed: std_logic;
signal download:boolean:=FALSE;
signal dump:boolean:=FALSE;
type data_file_t is file of character;
file datos: data_file_t open read_mode IS "./datos.txt";
signal watchdog:boolean:=FALSE;


begin
--ENTIDADES:
RAM: entity work.sram(behavior)
	generic map( size => 100 , adr_width => 18, width => 16)
	port map(
		nOE => oe_n,
		nWE => we_n,      
		nCE => ce_a_n,
		A => ad,
		D => dio_a,
		dump => dump
	);

boadTop0: entity work.BoardTop(arch)
	generic map(DVSR=>DVSR,W=>W,WORDS=>WORDS)
	port map(
		pulsador => (others =>'0'),
		xtal => clk,
		reset => reset,
		vsinc_o => open,	
		hsinc_o => open,
		red_o => open,
		green_o => open,
		blue_o => open,
		uart_rx => rx,
		uart_tx => tx,
		ad => ad,
		we_n => we_n,
		oe_n => oe_n,
		dio_a => dio_a,
		ce_a_n => ce_a_n,
		ub_a_n => open,
		lb_a_n => open,
		tx_done_tick => tx_done_tick,
		tx_start => tx_start,
		tx_din => tx_din,
		ad_restart => restart
		);





---SIMULATION BEGIN
clk<=not clk after 10 ns;
tx_start<=(done_delayed OR tx_start_bis) AND NOT mode;
tx_start_bis<='0' , '1' after 20 ns, '0' after 40 ns;
reset<='0', '1' after 10 ns, '0' after 20 ns;
rx<=tx;

test_sequence:process
	variable ch : character:='A';
	variable contador:integer:=0;
	constant vueltas:integer:=5; --CANTIDAD DE VECES QUE QUERES BARRER LA MEMORIA. --NO FUNCIONO
begin
	while not (endfile(datos)) loop
	wait until clk='1' and clk'event ;
		if tx_done_tick='1' then
			READ(datos, ch);
			tx_din<=std_logic_vector(to_unsigned(character'pos(ch),8));
		end if;
	end loop;
       	
	assert false report
                "Fin de Archivo" severity warning;

	wait until clk='1' and clk'event and tx_done_tick='1';
			ch:=character'val(27); -- <ESC>
			tx_din<=std_logic_vector(to_unsigned(character'pos(ch),8));
	file_close(datos);
	assert false report
		"Bajando Memoria" severity warning;
	dump<=TRUE;

	watchdog<=TRUE;
	--ALGO FALLA CON ESTO, PERO EL WATCHDOG FUNCIONA
	while  contador < vueltas LOOP
		wait until clk='1' and clk'event;
		if mode='1' and restart='1' then
		assert false report
				integer'image(contador) severity warning;
		end if;
	end loop;

	assert false report
		"Termine" severity failure;
	end process;

delayed: process(clk, reset)
		begin
		if reset = '1' then
		done_delayed<='0';
		elsif clk='1' and clk'event then
		done_delayed<=tx_done_tick;
		end if;
	end process;

watchdog0: process
		begin
		wait until watchdog=TRUE;
		wait for 500 us;
		assert false report
			"Watchdog Timeout" severity failure;
		end process;

end simul;
